Low power and Area Efficient System with Fast Error Correction using Pulsed Latch

Aggressive reduction of timing margins, called timing speculation, is an effective way of reducing the supply voltage for a pipeline circuit and thereby its power consumption. However, probability of timing error increases with the voltage scaling and hence, the errors must be corrected with small cycle penalty. Here introduce an improved Razor approach by replacing flip flop by pulsed latch, which makes more effective than others. The proposed method is a low-power and area-efficient system with fast error correction using small cycle penalty. The area and power consumption are reduced by using this method. This method solves the timing problem between pulsed latches through the use of multiple non-overlap delayed pulsed clock signals instead of the conventional single pulsed clock signal. So uses a delayed pulse clock generator. Which provides short delayed pulse signal to latches.